Table 1 Main characteristics of literature test-benches and differences with related work
From: A novel FPGA-based test-bench framework for SDI stream verification
Work | Type | Connectivity | Data available | Remarks |
|---|---|---|---|---|
[18] | Internal scan chain | N/A | Simulation time vs # of scan chain | Overheads in FPGA resources; limited observability to internal signals; the protocol observation is not allowed; its analysis time is fast |
[19] | Test-bench connected to the board | PCI to interchange data between DUT and PC | Simulation time, FPGA resources | Overheads in FPGA resources; limited observability to internal signals; the protocol observation is not allowed; its analysis time is fast with less probing nodes; became slow with a high number of probing nodes |
[22] | Software simulation and hardware emulation | UART and JTAG for debug | Debugging speed comparison, FPGA resources | Overheads in FPGA resources; limited observability to internal signals; the protocol observation is not allowed; its simulation time is fast |
[24] | Software simulation and hardware on FPGA IP verification | S-Video/VGA signal input and output, USB / RS232 for debug | Unknown-only structure | Overheads in FPGA resources; limited observability to internal signals; the protocol observation is not allowed; do not provide simulation/analysis time |
Our work | Software simulation | SDI family, but this method allows to use every interface to carry signals | Simulation time, simulated internal blocks processing time, FPGA resources | We do not overhead in FPGA resources; unlimited observability to internal and external signals; we allow protocol observation; it is integrable to any simulation tool; commercial or open source; the simulation time is slow |