- Open Access
Simplified spiking neural network architecture and STDP learning algorithm applied to image classification
© Iakymchuk et al.; licensee Springer. 2015
- Received: 30 April 2014
- Accepted: 28 January 2015
- Published: 19 February 2015
Spiking neural networks (SNN) have gained popularity in embedded applications such as robotics and computer vision. The main advantages of SNN are the temporal plasticity, ease of use in neural interface circuits and reduced computation complexity. SNN have been successfully used for image classification. They provide a model for the mammalian visual cortex, image segmentation and pattern recognition. Different spiking neuron mathematical models exist, but their computational complexity makes them ill-suited for hardware implementation. In this paper, a novel, simplified and computationally efficient model of spike response model (SRM) neuron with spike-time dependent plasticity (STDP) learning is presented. Frequency spike coding based on receptive fields is used for data representation; images are encoded by the network and processed in a similar manner as the primary layers in visual cortex. The network output can be used as a primary feature extractor for further refined recognition or as a simple object classifier. Results show that the model can successfully learn and classify black and white images with added noise or partially obscured samples with up to ×20 computing speed-up at an equivalent classification ratio when compared to classic SRM neuron membrane models. The proposed solution combines spike encoding, network topology, neuron membrane model and STDP learning.
- Spiking neural networks - SNN
- Visual receptive fields
- Spike coding
- Embedded system
- Artificial neuron
- Image classification
In the last years, the popularity of spiking neural networks (SNN) and spiking models has increased. SNN are suitable for a wide range of applications such as pattern recognition and clustering, among others.There are examples of intelligent systems, converting data directly from sensors [1,2], controlling manipulators  and robots , doing recognition or detection tasks [5,6], tactile sensing  or processing neuromedical data . Different neuron models exist  but their computational complexity and memory requirements are high, limiting their use in robotics, embedded systems and real-time or mobile applications in general.
Existing simplified bio-inspired neural models [10,11] are focused on spike train generation and real neuron modeling. These models are rarely applied in practical tasks. Some of the neuronal models are applied only for linearly separable classes  and focus on small network simulation.
Concerning hardware implementation, dedicated ASIC solutions exist such as SpiNNaker , BrainScaleS , SyNAPSE  or others , but they are targeted for large-scale simulations rather than portable, low-power and real-time embedded applications. The model we propose is mainly oriented for applications requiring low-power, small and efficient hardware systems. It can also be used for computer simulations with up to ×20 speed-up compared to classic SRM neuron membrane model. Nowadays, due to a continuous decrease in price and increase in computation capabilities, combined with the progress in high-level hardware description language (HDL) synthesis tools, configurable devices such as FPGA can be used as efficient hardware accelerators for neuromorphic systems. A proposal was made by Schrauwen and Van Campenhout  using serial arithmetic to reduce hardware resource consumption, but no training or weight adaptation was possible. Other solution, presented by Rice et al.  used full-scale Izhikevich neurons with very high resource consumption (25 neurons occupy 79% of logic resources in a Virtex4 FPGA device), without on-line training.
Computation methods used for FPGA dramatically differ from classic methods used in Von Neumann PCs or even SIMD processing units like GPUs or DSPs. Thus, the required SNN hardware architecture must be different for reconfigurable devices, opening new possibilities for computation optimization. FPGA are optimal for massive parallel and relatively simple processing units rather than large universal computational blocks as is in case of SNN, including lots of multiply-add arithmetic blocks and vast quantities of distributed block RAM . This work describes computation algorithms properly modeling the SNN and its training algorithm, specifically targeted to benefit from reconfigurable hardware blocks. The proposed solution combines spike encoding, topology, neuron membrane model and spike-time dependent plasticity (STDP) learning.
Spiking neural networks are considered to be the third generation of artificial neural networks (ANN). While classic ANN operate with real or integer-valued inputs, SNN process data in form of series of spikes called spike trains, which, in terms of computation means that a single bit line toggling between logical levels ‘0’ and ‘1’ is required. SNN are able to process temporal patterns, not only spatial, and SNN are more computationally powerful than ANN . Classic machine learning methods perform poorly for spike coded data, being unsuitable for SNN. As a consequence, different training and network topology optimization algorithms must be used [9,21].
The SNN model used in this work is the feed-forward network, each neuron is connected to all the neurons in the next layer by a weighted connection, which means that the output signal of a neuron has a different weighted potential contribution . Input neurons require spike trains and input signals (stimuli) need to be encoded into spikes (typically, spike trains) to further feed the SNN.
An approximation to the functionality of a neuron is given by electrical models which reproduce the functionality of neuronal cells. One of the most common models is the spike response model (SRM) due to the close approximation to a real biological neuron [23,24]; the SRM is a generalization of the ‘integrate and fire’ model . The main characteristic of a spiking neuron is the membrane potential, the transmission of a single spike from one neuron to another is mediated by synapses at the point where neurons interact. In neuroscience, a transmitting neuron is defined as a presynaptic neuron and a receiving neuron as a postsynaptic neuron. With no activity, neurons have a small negative electrical charge of −70 mV, which is called resting potential; when a single spike arrives into a postsynaptic neuron, it generates a post synaptic potential (PSP) which is excitatory when the membrane potential is increasing and inhibitory when decreasing. The membrane potential at an instant is calculated as the sum of all present PSP at the neuron inputs. When the membrane potential is above a critical threshold value, a postsynaptic spike is generated, entering the neuron into a refractory period when the membrane remains overpolarized, preventing neurons from generating new spikes temporarily. After a refractory period, the neuron potential returns to its resting value and is ready to fire a new spike if membrane potential is above the threshold.
These equations define the SRM, which can be modeled by analog circuits since the PSP function can be seen as a charging and discharging RC circuit. However, this model is computationally complex when used in digital systems. We propose to use a simplified model with linear membrane potential degradation with similar performance and learning capabilities as the classic SRM.
Thus, instead of an initial postsynaptic potential ramp in the spike response model, the instant change of membrane potential allows a neuron to fire immediately in the next clock cycle after the spike arrives.
3.1 Spike-time dependent plasticity learning
Since unsupervised learning requires competition, lateral inhibition was introduced and thus, the weights of the winner neurons (first spiking neurons) are increased while other neurons suffer a small weight reduction value. Tests showed that depressing the weights of the non firing neurons decrease the amount of noise in the network. The depression of synapses that do not fire at all was added in order to eliminate ‘mute’ synapses (inactive synapses), reducing the network size and improving robustness against noise. This training causes a side effect since, for weight increase, spike-intense patterns require a higher membrane threshold, avoiding the patterns with low spike intensity to be recognized by the network. This is solved by introducing negative weights, preventing neurons from reacting on every pattern and increasing the specificity of classifier.
The visual cortex is one of the best studied parts of the brain. The receptive field (RF) of a visual neuron is an area of the image affecting the neural input. The size and shape of receptive fields vary depending on the neuron position and neuron task. A variety of tasks can be done with RFs: edge detection, sharpening, blurring, line decomposition, etc. In each subsequent layer of the visual cortex, receptive fields of the neurons cover bigger and bigger regions, convolving the outputs of the previous layer.
Mammalian retinal ganglion cells located at the center of vision, in the fovea, have the smallest receptive fields, and those located in the visual periphery have the largest receptive fields . The large receptive field size of neurons in the visual periphery explains the poor spatial resolution of human vision outside the point of fixation, together with photoreceptor density and optical aberrations. Only a few cortical receptive fields resemble the structure of thalamic receptive fields, some fields have elongated subregions responding to dark or light spots, while others do not respond to spots at all. In addition, the implementation of a receptive field is a first stage of sparse coding  where the neurons are reacting to shapes, not single pixels. The receptive field model proposed here shows a good approximation to the real behavior of primary visual cortex.
4.1 Receptive field neuron response
5.1 Image encoding
5.2 Network architecture
The proposed SNN consists of 2 layers, an encoding layer of 256 neurons with an on-centered 5 × 5 pixel RF and second layer of 16 neurons using the simplified SRM. Experimental testing showed that, for proper competitiveness in the network, the number of neurons should be at least 20% greater than the number of classes and thus, 16 neurons were implemented. If the number of neurons is insufficient, only the most spike-intensive patterns are learnt. Each sample was presented to the network during 200 time units (TUs). With a refractory period of encoding neurons of 30 TUs, the maximum possible amount of spikes is 200/30 = 6. STDP parameters for learning were A +=0.6,A −=0.3,τ +=8,τ −=5. The maximum weight change rate σ was fixed to 0.25∗max(STDP)=0.25∗0.25=0.0625.
For the classic SRM algorithm, a table-based PSP function of 30 points was used (simplified model uses constant decrease as PSP and does not require table-based functions). For both SRM and simplified models, STDP function was also table-based with 30 positive and 30 negative values. All algorithms (classic and simplified model) were written using atomic operations without the usage of Matlab vector and matrix arithmetic. Such coding style provides more accurate results in performance tests when modeling hardware implementation.
Simulation speed of classic and simplified networks
5 classes, 8 neurons, 15,000 time units
6 classes, 9 neurons, 15,000 time units
6 classes, 16 neurons, 15,000 time units
6 classes, 100 neurons, 15,000 time units
12 classes, 50 neurons, 96,000 time units
In this paper, we describe a simplified spiking neuron architecture optimized for embedded systems implementation, proving the learning capabilities of the design. The network preserves its learning and classification properties while computational and memory complexity is reduced dramatically - by eliminating the PSP table in each neuron. Learning is stable and robust, the trained network can recognize noisy patterns. A simple, yet effective visual input encoding was implemented for this network. The simplification is beneficial for reconfigurable hardware systems, keeping generality and accuracy. Furthermore, slight modifications would allow to be used with Address-Event Representation (AER) data protocol for frameless vision . The proposed system could be further implemented in FPGAs for low-power embedded neural computation.
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