Table 2 Cortex-A9 and Cortex-A15 comparison
From: A novel architecture for parallel multi-view HEVC decoder on mobile device
Cortex-A9 | Cortex-A15 | |
|---|---|---|
Instruction set | ARMv7 | ARMv7 (virtual 40b PA) |
Core Config. | 1, 2, 4 | 2, 4, 8 (4 × 2) |
Speed per core (DMIPS/MHz) | 2.5 | 3.5 to 4.01 |
L1 cache (KB) | 32 + 32 | 32 + 32 |
L2 cache (MB) | 1 | Up to 4 |
Data Bus (bit) | 32 | 32 |
SIMD Engine | ARM NEON (64 bit) | ARM NEON (128 bit) |
Decoder width | 2 | 3 |
Pipeline depth | 8–11 | 15/17–25 |
FPU | VFPv3 | VFPv4 |