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Table 4 The number of clock cycles to process one frame with an SRP simulator

From: A parallel camera image signal processor for SIMD architecture

Module

Sequential

Parallel

WB

11,892,670

2,651,547

Modified AHD

45,935,860

12,695,570

Color correction/RGB to YCoCg/Y min,max

45,555,149

10,265,334

Modified BF (3 × 1)/AC

46,810,082

5,946,081

Modified BF (1 × 3)

30,112,720

5,154,872

Modified LTI (1 × 3)

21,785,128

3,220,328

YCoCg to RGB/GC

38,521,495

9,146,287

Total

240,609,434

49,080,019