Table 3 Device utilization and timing summary of DCT architecture with and without comparison block
From: Implementation of computation-reduced DCT using a novel method
Hardware utilization | Chen’s algorithm | Lee’s algorithm | ||
|---|---|---|---|---|
With comparative block. | Without comparative block. | With comparative block. | Without comparative block. | |
Number of slices (4656) | 255 | 193 | 165 | 103 |
Number of four input LUTs (9312) | 428 | 373 | 242 | 187 |
Number of bonded IOBs (190) | 138 | 136 | 138 | 136 |
Maximum combinational path delay (ns) | 22.542 | 21.603 | 21.238 | 20.297 |