From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform
Architecture
Memory
For j= 1
For j= 5
Aziz[15]
4N
4N+2N+N+ N 2 + N 4 ≈7.7N
PMA
2N
2N+ 3 N 2 + 3 N 4 + 3 N 8 + 3 N 16 ≈4.8N