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Table 8 Comparison of hardware and time complexity of the proposed PMA for lifting (5, 3) filter

From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Architecture

Multipliers/

Adders/

Memory j= 1

Computing

Latency

Critical

HUE (%)

 

shifters

subtractors

On-chip

Off-chip

cycle for j level

j = 1

path delay

 

Hasan[23]

2j

j

3N

0

O(N2)

3N

2Ta + Ts

100

Aziz[15]

2j

4j

4N

0

∑ m = 1 j 1 + 3 N 2 m - 1 + N 2 2 2 ( m - 1 )

3N + 1

2Ta

50 to 60

PMA

4 + 6(j - 1)

8 + 12(j - 1)

2N

0

2+ ∑ m = 1 j 10 + N 2 m - 1 + N 2 2 2 m - 1

N + 12

Ta + Ts

60 to 75

  1. Input image size N × N and j ≥ 1. Ta, adder delay; Tm, multiplier delay; Ts, shifter delay; j, level of decomposition.