From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform
Architecture
Multipliers/
Adders/
Memory j= 1
Computing
Latency
Critical
HUE (%)
shifters
subtractors
On-chip
Off-chip
cycle for j level
j = 1
path delay
Hasan[23]
2j
j
3N
0
O(N2)
2Ta + Ts
100
Aziz[15]
4j
4N
∑ m = 1 j 1 + 3 N 2 m - 1 + N 2 2 2 ( m - 1 )
3N + 1
2Ta
50 to 60
PMA
4 + 6(j - 1)
8 + 12(j - 1)
2N
2+ ∑ m = 1 j 10 + N 2 m - 1 + N 2 2 2 m - 1
N + 12
Ta + Ts
60 to 75