High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

EURASIP Journal on Image and Video Processing

Table 7 Comparison of hardware and time complexity of the proposed FMA for lifting (9, 7) filter

Architecture	Multipliers/	Adders/	Memory		Output	Computing	Critical	HUE (%)
	shifters	subtractors	On-chip	Off-chip	latency	time for j level	path delay
Andra[8]	32	32	N ²	0	N²/2	4N²(1 - 4^-j)/3	4Ta + 2Tm	100
Wu[3]	6	8	5.5N	N²/4	∼	2N²(1 - 4^-j)/3	Tm	100
Barua[22]	12	16	7N	N²/4	7N	2N²(1 - 4^-j)/3	2Ta + Tm	100
Xiong[13] FA	10	16	5.5N	N²/4	2N	2N²(1 - 4^-j)/3	2Ta + Tm	100
Xiong[13] HA	18	32	5.5N	N²/4	N	N²(1 - 4^-j)/3	2Ta + Tm	100
FMA	10	16	4N	N²/4	N	2N²(1 - 4^-j)/3	Ta + Tm	100

Input image size N × N and j ≥ 1. Ta, adder delay; Tm, multiplier delay; Ts, shifter delay; ∼, not available.