EURASIP Journal on Image and Video Processing

Table 6 Hardware and time complexity comparison of the proposed FMA for lifting (5, 3) filter

From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Architecture	Multipliers/	Adders/	Memory		Computing	Output	Critical	HUE (%)
	shifters	subtractors	On-chip	Off-chip	time for j level	latency	path delay
Andra[8]	4	8	N² + 4N	0	2N²(1 - 4^-j)/3	2N	2Ta + 2Ts	100
Wu[3]	4	8	5N	N²/4	2N²(1 - 4^-j)/3	2N	2Ta + Tm	100
Barua[22]	4	8	5N	N²/4	2N²(1 - 4^-j)/3	5N	Tm	100
Xiong[13] FA	4	8	3.5N	N²/4	2N²(1 - 4^-j)/3	N	2Ta + Tm	100
Xiong[13] HA	8	16	3.5N	N²/4	N²(1 - 4^-j)/3	N	2Ta + Tm	100
FMA	4	8	2N	N²/4	2N²(1 - 4^-j)/3	N	Ta + Ts	100

Input image size N × N and j ≥ 1. Ta, adder delay; Tm, multiplier delay; Ts, shifter delay.

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