EURASIP Journal on Image and Video Processing

Table 5 Performance comparison of 2-D DWT architectures

From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Architecture	Mul.	Add.	Buff.	C.P.	Thr.	C.C.	HUE (%)
DSA[10]	12	16	4N	4T_m + 8T_a	1	N²/2	100
Wu[3]	6	8	4N	T _m	1	N ²	100
FA[13]	10	16	5.5N	T_m + 2T_a	2	N²/2	100
HA[13]	18	32	5.5N	T_m + 2T_a	4	N²/4	100
Lai[4]	10	16	4N	T _m	2	N²/2	100
Zhang[5]	10	16	4N	T _m	2	N²/2	-
Hsia[6]	0	16	4N	2T_m + 4T_a	2	3N²/4	-
Darji[7]	10	16	4N	T _m	2	N²/2	100

Mul., multipliers; Add., adders; Buff., buffers; C.P., critical path; Thr., throughput; C.C., computational cycle; P, parallel factor; HUE, hardware utilization efficiency.

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