Table 14 FPGA synthesis results of the proposed PMA for lifting (5, 3) 2-D DWT
From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform
Architecture | Power for j= 1 (mW) | Frequency | CLB slice count | Throughput frames/s | |||
|---|---|---|---|---|---|---|---|
| Â | Dynamic | Quiescent | Total | Â | For j = 1 | For j = 5 | Â |
Aziz[15] | 33.85 | 1,186.94 | 1,220.79 | 221.44 | 206 | 1,052 | 835 |
PMA without clk gating | 29.6 | 980.8 | 1,010.6 | 539 | 412 | 1,329 | 4,080 |
PMA with clk gating | 28 | 980.8 | 1,008.2 | 539 | 342 | 1,178 | 4,080 |