From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform
Arch.
Mult.
Add.
Line buffers
Control complexity
Computing time
Liao[10]
12
16
10N(1 - 2-j)
Medium
N2/2
Xiong[16]
28
48
10N(1 - 2-j) + 0.5N
N2/4
RMA
24
12.5N
Simple