EURASIP Journal on Image and Video Processing

Table 11 Hardware and time complexity of the proposed RMA

From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Architecture	Mult./	Add./	Memory j= 1		Output	Critical	HUE (%)
	shift.	sub.	On-chip	Off-chip	latency	path delay
RMA (5, 3)	6	12	6.5N	0	2N	2Ta + Tm	75
RMA (9, 7)	16	24	12.5N	0	4N	2Ta + Tm	75

Input image size N × N and j ≥ 1. Ta, adder delay; Tm, multiplier delay; Ts, shifter delay.

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