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EURASIP Journal on Image and Video Processing

Table 1 Data flow of predict/update module

From: High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Clock

Input

D1

D2

P/U

1

X1,1:X1,3:X1,2

   

2

X1,3:X1,5:X1,4

X1,1 + X1,3

X 1,2

 

3

X1,5:X1,7:X1,6

X1,3 + X1,5

X 1,4

P/U1,1

4

X1,7:X1,9:X1,8

X1,5 + X1,7

X 1,6

P/U1,2

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