Power-optimized log-based image processing system

EURASIP Journal on Image and Video Processing

Table 8 Comparison of B9/7 DWT implementation on FPGA

Architecture	Image size ( N)	Combinational functions	Logic register	Memory (bits)	F_max(MHz)
Barua [4]	1,024	3,938	2,727	114,688	65.37
Cheng and Parhi[11]	1,024	12,330	8,070	491,520	58.73
Tian (M = 2)[12]	1,024	3,180	2,378	81,920	65.38
Our work	256	2,416	235	71,445	58.65