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Table 1 Synthesis results

From: Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission

  Virtex II Virtex V Virtex VI Virtex VII
  (2vp30ff896-7) (5vlx30ff676-3) (6vcx75tff784-2) (7vx330tffg1157-3)
Selected device     
 Slices LUTs 2,067 (15%) 4,721 (24%) 3,238 (6%) 3,238 (1%)
 Slice registers 1,150 (4%) 1,105 (5%) 1,100 (1%) 1,100 (< 1%)
 IOBs 130 (23%) 130 (32%) 130 (36%) 130 (21%)
 MULT18X18s 36 (26%) - - -
 DSP48Es - 20 (62%) 60 (20%) 60 (5%)
 GCLKs 1 (6%) 1 (3%) 1 (3%) 1 (3%)
Maximum frequency (MHz) 25.364 36.271 28.507 35.842