Figure 4From: Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission Architecture of the hyperchaotic Lorenz generator module. The four outputs S 0, S 1, S 2, and S 3 are the hyperchaotic signals, encoded on 32-bit (16Q16) fixed-point data format. The two inputs, clk and reset, are the clock signal and the reset signal, respectively.Back to article page