Table 7 Additional hardware specifications used in our system
From: Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array
| Â | Spec. (Resource usage percentage) |
|---|---|
FPGA | Xilinx Virtex II pro-100 |
Number of multiplier | 0 |
Number of divider | 0 |
Number of slice flip flops | 30,585 (34%) |
Number of 4 input LUTs | 46,812 (53%) |