Table 6 Comparisons of hardware spec. between the real-time systems
From: Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array
Spec | System | clock | PEs | Int. Mem. | Ext. Mem. |
|---|---|---|---|---|---|
Our FBP, One FPGA | Virtex2 | 25 MHz | 128 | 3.3 Mb | No |
Two FPGAs | Virtex2 | 25 MHz | 256 | 6.6 Mb | No |
Semi-global matching [17] | Virtex5 | 133 MHz | 30 | 3.3 Mb | Yes |
Local matching [22] | Virtex5 | 93 MHz | 64 | 5.8 Mb | No |
Real-time BP [13] | Geforce 7900 | 670 MHz | 26 | NA | 62 Mb |
Accelerated BP[21] | Virtex2 | 65 MHz | 24 | 2 Mb | 9 Mb |
Real-time DP [20] | MMX | NA | NA | NA | Yes |
Trellis DP [19] | Virtex2 | 50 MHz | 128 | Yes | No |