Table 8 The bayer filter core: exploration of pipeline optimization space
From: Pipeline synthesis and optimization of FPGA-based video processing applications with CAL
N stage | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|
T stage | 8.30 | 5.32 | 4.30 | 3.22 | 3.10 | 3.00 |
Reg-width asap | 215 | 453 | 737 | 998 | 1259 | 1428 |
Reg-width alap | 308 | 501 | 710 | 949 | 1273 | 1383 |
Reg-width best | 147 | 340 | 487 | 680 | 972 | 1095 |
Reg-width worst | 376 | 660 | 1013 | 1320 | 1650 | 1658 |
Reg-width reduction (%) | 156.0 | 94.0 | 108.0 | 94.1 | 69.8 | 51.4 |
Feasible schedules | 1440 | 264384 | > 1010 | > 1010 | > 1010 | > 1010 |