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Table 7 The 8 × 8 1D IDCT: exploration of pipeline optimization space

From: Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

N stage 2 3 4 7
T stage 4.00 3.00 2.00 1.00
Reg-width asap 364 520 832 1664
Reg-width alap 312 624 832 1716
Reg-width best 260 468 832 1664
Reg-width worst 494 884 1196 2028
Reg-width reduction (%) 90.0 88.9 43.8 21.9
Feasible schedules 24336 29555604 63002926 4505752
Cut branches 592 1803470 12295281 1298947
Complete schedules 5 3 1 1