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Figure 10 | EURASIP Journal on Image and Video Processing

Figure 10

From: An FPGA-based processing pipeline for high-definition stereo video

Figure 10

Data path details of one matching stage. For illustration purposes, a simplified example with a matching window size of 3 × 3 pixels and a disparity search range of 4 pixels is shown. Furthermore, only one matching direction is shown (e.g., only left-right match). The illustration on the left side shows a high-level overview of one matching level. Note that the downsampling operation reduces the data rate to 1 4 . A fully parallel implementation (top-right illustration) would therefore be un-utilized for many cycles. We employ time-sharing (lower-right illustration) using one single matching unit only, which is fully utilized for every cycle without reducing the throughput. Note that the design is parameterized, and the amount of time-sharing is configurable at compile-time.

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