Table 3 Comparison with the introduced system in [ [19]]
From: Real-time lane departure warning system based on a single FPGA
Module | System in [19] | This paper | |||
|---|---|---|---|---|---|
Function | Lane track | Lane track + warning | |||
Platform | Xilinx Spartan-3A DSP 3400 | Xilinx Spartan-3A DSP 3400 | |||
Tools | System generator for DSP (Rel. 10.1.3) | ISE 11.4 | |||
Language | System generator scheme | VHDL | |||
Power (volt/watt) | Not mentioned | 5V/2W | |||
LDWS size (millimeter) | Not mentioned | 100×75 × 20 | |||
Image size | 752 × 480 | 752 × 320 | |||
Frequency(frame/s) | 30 | 40 | |||
Line detection method | Model fitting | Proposed Hough transform | |||
External memory used | Not mentioned | No | |||
Tracking unit | Special designed by HDL | Working in MicroBlaze | |||
Resource | Preprocess | DSP48 | 12 (9%) | 5 (4%) | |
BRAM | 16 (12%) | 6 (5%) | |||
Slices | 2,594 (10%) | 2,601 (10%) | |||
Line detection | DSP48 | 17 (13.5%) | 16 (12.7%) | ||
BRAM | 14 (11.1%) | 40 (31.7%) | |||
Slices | 3,120 (13.1%) | 1,091 (4%) | |||
T&W | DSP48 | 5 (4%) | 4 (3%) | ||
BRAM | 2 (1.6%) | 64 (50.8%) | |||
Slices | 2,686 (11.2%) | 2,144 (9%) | |||
DCM clock manager | Not mentioned | 3 | |||