Table 1 Time and resources occupation of the proposed LDWS
From: Real-time lane departure warning system based on a single FPGA
Module | CC | CC + EE | CC + EE + VPPHT | CC + EE + VPPHT + TRW | |
|---|---|---|---|---|---|
Time (ms) (average) | 9.24 | 9.32 | 13.92 | 25 | |
Resource | Total LUTs | 1,944 (4%) | 2,901 (6%) | 4,632 (9.7%) | 8,793 (18%) |
Flip flops | 2,936 (6%) | 3,762 (7.8%) | 4,966 (10%) | 7,085 (15%) | |
Block RAM | 0 | 6 (5%) | 46 (37%) | 110 (87%) | |
DSP48 | 3(2%) | 5 (4%) | 21 (16%) | 25 (19%) |