Table 5 Comparisons of computation time between the real-time systems
From: Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array
Spec | System | Image | Levels | fps |
|---|---|---|---|---|
Our FBP, One FPGA | FPGA, Virtex2 | 160 × 480 | 32 | 15 |
Two FPGAs | FPGA, Virtex2 | 320 × 480 | 32 | 15 |
Semi-global matching [17] | FPGA, Virtex5 | 640 × 480 | 128 | 103 |
Local matching [22] | FPGA, Virtex5 | 640 × 480 | 64 | 230 |
Accelerated BP [21] | FPGA, Virtex2 | 256 × 240 | 16 | 25 |
Real-time BP [13] | GPU, Geforce 7900 | 320 × 240 | 16 | 16 |
Real-time DP [20] | CPU, MMX | 320 × 240 | 100 | 26.7 |
Trellis DP [19] | FPGA, Virtex2 | 320 × 240 | 128 | 30 |